The invention relates to a method of testing integrated circuits provided on a carrier. In the method, a test pattern is presented serially to an integrated circuit set to an input state, by means of a first connection of the integrated circuits. The test pattern is stored temporarily. The integrated circuits are set to an execution state to form a result pattern from the test pattern. The result pattern present in any of the integrated circuits set to an output state is then serially removed by means of a second connection of the integrated circuits to provide, by means of an evaluation on the information contents thereof, a characterization of a correct/incorrect operation of the integrated circuits and their interconnection function, respectively. An example of such carriers comprises printed circuit boards, but the invention is not restricted to the interconnection technology. With integrated circuits becoming more and more complex, the need for a reliable test method increases because rejection of a product in an earlier phase of production is usually much less expensive than rejection in a later production phase. An integrated circuit can be tested exhaustively before being mounted on such a carrier so that the possibility of an undetected defect in such an integrated circuit is negligibly small. Nevertheless, testing of the carrier with mounted circuits in a structure test proves to be useful because an integrated circuit may be damaged during mounting and because an interconnection function may be defective.
The interconnection function between two (or more) integrated circuits is to be understood to mean the operational behaviour and hence implicitly the correct/incorrect structure of the following elements or a part thereof, for example:
a. the conductor pattern provided on the carrier: test for interruption and/or short circuit; PA0 b. the connection between said conductors and the connection pins of the integrated circuit modules: PA0 c. the connection between said connection pins and the bonding flaps provided on the substrate of the integrated circuit, for example by means of a bonding wire; PA0 d. optionally present buffer elements between the bonding flap and the input/output for the relevant bit of test/result pattern; PA0 e. optional further elements provided between the integrated circuits thus connected, at least as far as their digital functioning is concerned. They may be passive elements, for example a terminating resistor which couples an interconnection junction to earth. Alternatively, they may be an integrated circuit which in itself cannot be tested, for example a module constructed in conventional TTL logic, for example a latch circuit.